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refactor: renames memory/disk size fields to use MiB in app proto

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This commit is contained in:
Noor 2025-06-25 18:33:13 +05:30
parent 6d37792640
commit 2fb91e5e87
Signed by: noormohammedb
GPG Key ID: D83EFB8B3B967146
3 changed files with 13 additions and 14 deletions
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3
Cargo.lock generated
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@ -1,7 +1,6 @@
# SPDX-License-Identifier: Apache-2.0
# This file is automatically @generated by Cargo.
# It is not intended for manual editing.
# SPDX-License-Identifier: Apache-2.0
version = 4
[[package]]

12
proto/sgx/app.proto
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@ -38,8 +38,8 @@ message NewAppReq {
}
message AppResource {
uint32 memory_mb = 1;
uint32 disk_size_gb = 2;
uint32 memory_mib = 1;
uint32 disk_size_mib = 2;
uint32 vcpus = 3;
repeated uint32 ports = 4;
}
@ -66,8 +66,8 @@ message ListAppContractsReq {
message AppNodeFilters {
uint32 vcpus = 1;
uint32 memory_mb = 2;
uint32 storage_gb = 3;
uint32 memory_mib = 2;
uint32 storage_mib = 3;
string country = 4;
string region = 5;
string city = 6;
@ -112,8 +112,8 @@ message AppNodeResources {
string node_pubkey = 1;
uint32 avail_no_of_port = 2;
uint32 avail_vcpus = 3;
uint32 avail_memory_mb = 4;
uint32 avail_storage_gb = 5;
uint32 avail_memory_mib = 4;
uint32 avail_storage_mib = 5;
uint32 max_ports_per_app = 6;
}

12
src/sgx/types/brain.rs
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@ -7,8 +7,8 @@ use serde::{Deserialize, Serialize};
#[derive(Debug, Clone, Serialize, Deserialize, PartialEq, Default)]
pub struct Resource {
pub memory_mb: u32,
pub disk_size_gb: u32,
pub memory_mib: u32,
pub disk_size_mib: u32,
pub vcpus: u32,
pub port: Vec<u32>,
}
@ -16,8 +16,8 @@ pub struct Resource {
impl From<AppResource> for Resource {
fn from(pb_val: AppResource) -> Self {
Self {
memory_mb: pb_val.memory_mb,
disk_size_gb: pb_val.disk_size_gb,
memory_mib: pb_val.memory_mib,
disk_size_mib: pb_val.disk_size_mib,
vcpus: pb_val.vcpus,
port: pb_val.ports,
}
@ -26,8 +26,8 @@ impl From<AppResource> for Resource {
impl From<Resource> for AppResource {
fn from(val: Resource) -> AppResource {
AppResource {
memory_mb: val.memory_mb,
disk_size_gb: val.disk_size_gb,
memory_mib: val.memory_mib,
disk_size_mib: val.disk_size_mib,
vcpus: val.vcpus,
ports: val.port,
}