2553298b1d
Init support for cpuid and rdtsc instruction handling in occlum. This patch includes: 1. cpuid exception handler for all information leaves; 2. rdtsc exception handler; 3. handler registration; 4. cpuid test; 5. rdtsc test. Signed-off-by: 散樗 <kailun.qkl@antfin.com>
94 lines
3.4 KiB
C
94 lines
3.4 KiB
C
#include <stdio.h>
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#include <stdint.h>
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typedef struct t_cpuid {
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unsigned int eax;
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unsigned int ebx;
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unsigned int ecx;
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unsigned int edx;
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} t_cpuid_t;
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static inline void native_cpuid(int leaf, int subleaf, t_cpuid_t *p)
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{
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/* ecx is often an input as well as an output. */
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asm volatile("cpuid"
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: "=a" (p->eax),
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"=b" (p->ebx),
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"=c" (p->ecx),
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"=d" (p->edx)
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: "a" (leaf), "c" (subleaf));
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}
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int main(int argc, char **argv)
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{
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/* Gets CPUID information and tests the SGX support of the CPU */
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t_cpuid_t cpu = {0};
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int leaf = 1;
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int subleaf = 0;
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native_cpuid(leaf, subleaf, &cpu);
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printf("eax: %x ebx: %x ecx: %x edx: %x\n", cpu.eax, cpu.ebx, cpu.ecx, cpu.edx);
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printf("Stepping %d\n", cpu.eax & 0xF); // Bit 3-0
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printf("Model %d\n", (cpu.eax >> 4) & 0xF); // Bit 7-4
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printf("Family %d\n", (cpu.eax >> 8) & 0xF); // Bit 11-8
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printf("Processor Type %d\n", (cpu.eax >> 12) & 0x3); // Bit 13-12
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printf("Extended Model %d\n", (cpu.eax >> 16) & 0xF); // Bit 19-16
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printf("Extended Family %d\n", (cpu.eax >> 20) & 0xFF); // Bit 27-20
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// if smx (Safer Mode Extensions) set - SGX global enable is supported
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printf("smx: %d\n", (cpu.ecx >> 6) & 1); // CPUID.1:ECX.[bit6]
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/* Extended feature bits (EAX=07H, ECX=0H)*/
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printf("\nExtended feature bits (EAX=07H, ECX=0H)\n");
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leaf = 7;
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subleaf = 0;
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cpu = {0};
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native_cpuid(leaf, subleaf, &cpu);
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printf("eax: %x ebx: %x ecx: %x edx: %x\n", cpu.eax, cpu.ebx, cpu.ecx, cpu.edx);
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//CPUID.(EAX=07H, ECX=0H):EBX.SGX = 1,
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// Bit 02: SGX. Supports Intel® Software Guard Extensions (Intel® SGX Extensions) if 1.
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printf("SGX is available: %d\n", (cpu.ebx >> 2) & 0x1);
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/* SGX has to be enabled in MSR.IA32_Feature_Control.SGX_Enable
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check with msr-tools: rdmsr -ax 0x3a
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SGX_Enable is Bit 18
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if SGX_Enable = 0 no leaf information will appear.
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for more information check Intel Docs Architectures-software-developer-system-programming-manual - 35.1 Architectural MSRS
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*/
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/* CPUID Leaf 12H, Sub-Leaf 0 Enumeration of Intel SGX Capabilities (EAX=12H,ECX=0) */
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printf("\nCPUID Leaf 12H, Sub-Leaf 0 of Intel SGX Capabilities (EAX=12H,ECX=0)\n");
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leaf = 0x12;
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subleaf = 0;
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cpu = {0};
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native_cpuid(leaf, subleaf, &cpu);
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printf("eax: %x ebx: %x ecx: %x edx: %x\n", cpu.eax, cpu.ebx, cpu.ecx, cpu.edx);
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printf("Sgx 1 supported: %d\n", cpu.eax & 0x1);
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printf("Sgx 2 supported: %d\n", (cpu.eax >> 1) & 0x1);
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printf("MaxEnclaveSize_Not64: %x\n", cpu.edx & 0xFF);
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printf("MaxEnclaveSize_64: %x\n", (cpu.edx >> 8) & 0xFF);
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/* CPUID Leaf 12H, Sub-Leaf 1 Enumeration of Intel SGX Capabilities (EAX=12H,ECX=1) */
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printf("\nCPUID Leaf 12H, Sub-Leaf 1 of Intel SGX Capabilities (EAX=12H,ECX=1)\n");
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leaf = 0x12;
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subleaf = 1;
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cpu = {0};
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native_cpuid(leaf, subleaf, &cpu);
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printf("eax: %x ebx: %x ecx: %x edx: %x\n", cpu.eax, cpu.ebx, cpu.ecx, cpu.edx);
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int i;
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for (i=2; i<4; i++) {
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/* CPUID Leaf 12H, Sub-Leaf i Enumeration of Intel SGX Capabilities (EAX=12H,ECX=i) */
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printf("\nCPUID Leaf 12H, Sub-Leaf %d of Intel SGX Capabilities (EAX=12H,ECX=%d)\n", i, i);
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leaf = 0x12;
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subleaf = i;
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cpu = {0};
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native_cpuid(leaf, subleaf, &cpu);
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printf("eax: %x ebx: %x ecx: %x edx: %x\n", cpu.eax, cpu.ebx, cpu.ecx, cpu.edx);
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}
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return 0;
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}
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